CI/CD: Firmware Pipeline Design

CI/CD: Firmware Pipeline Design

A first pipeline that compiles is not a release process. This subject is designing a pipeline that matches firmware reality: host tests vs. hardware-in-the-loop, artefacts (.elf / .bin), version stamps, and optional deploy-to-device on a dedicated runner. You keep secrets and signing keys out of the YAML.

Starting Points

• CI/CD basics
• GitLab Docs. CI/CD YAML syntax.
• Your MCU vendor's notes on headless builds (ESP-IDF, STM32Cube, PlatformIO).

Key Points

• You split jobs so a documentation-only change does not require a hardware runner.
• You publish build artefacts and a version identifier (git SHA) with the firmware image.
• You add at least one quality gate (compiler warnings-as-errors, unit tests, or a static check).
• You document how a human flashes a tagged build, even if CI does not touch the robot.
• You explain what you would need for true hardware-in-the-loop and why the studio pipeline may stop short of that.